As fin pitch scales down, it is more difficult to etch away the sacrificial fin hard masks used to guarantee active fin accuracy. In addition, as fins are formed there are non-idealities in terms of critical dimension variations, overlay variations, and resist pull-back during hard mask etch and post lithography expose. Uncut or partially cut fins can cause failures such as gate shorts, epi shorts, or isolation shorts. Currently, fin hard masks are typically made of oxide and SiN bilayers and have a height of approximately 70-120 nm at the time of cutting. Thus, the fin hard masks are tall relative to the ever decreasing fin pitch, which was previously between 48 nm and 60 nm, is currently between 36 nm and 42 nm, and is moving towards sub-30 nm, while the fin width is not scaling at the same rate, and fundamentally cannot scale below 8-10 nm during patterning. If the hard masks are scaled, material selectivity between the oxide, nitride, and silicon may occur. In addition, the current height of the hard masks may result in pullback during hard mask removal. Thus, a thinner hard mask is needed to prevent pullback and improve the fin cut accuracy. However, the currently used nitride hard mask material has a fundamental etch selectivity limitation between the poly, oxide, and nitride preventing it from being used as a hard mask in a thinner layer.
Thus, the fabrication of FinFET devices with tight pitches can be problematic with existing substrates and designs and improved substrates and FinFET device designs are needed for forming FinFET devices with tight fin pitches that maintain the current electrical performance of the resultant semiconductor devices.